Distributed multiprocessor communication system

Abstract

A distributed multiprocessor communication system, wherein the central processing unit (CPU) is relieved of the burden of bus management by a scheme which multiplexes the interprocessor module communications bus, to which all processors are guaranteed access, so that only an addressed CPU may be interrupted from performing its dedicated data processing function. Associated with each independent processor is a communications interface unit or communications network routing unit which relieves the processor of the task of decoding communications on the interprocessor or intermodule communications bus and, in addition, upon decoding its address and buffering message data, transmits a 'handshake' signal over the bus back to the sender during a designated time slot, thereby informing the sender that the transmitted message was actually received. Moreover, if one module is in a high priority mode of communication with another module, all lower priority messages are prevented from entering that particular module; yet, any other pairs of modules may still communicate. In other words, no module can possibly tie up the bus, preventing other modules from communicating. Once the data is placed onto the bus, under CPU direction, the transmission, reception, priority discrimination, and handshake are completely independent on CPU operation so that the time required to transfer a byte of data is independent of any processor in the system.