The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 1980

Filed:

Feb. 21, 1979
Applicant:
Inventor:

Eiichi Ishii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
455205 ; 455155 ; 455212 ; 455226 ;
Abstract

A signal processing circuit for an FM signal receiver suitable for constructing in an integrated circuit is disclosed. The signal processing circuit comprises a differential amplifier circuit receiving first and second demodulated signals of the frequency modulated signal and providing first and second output signals. A current switching circuit has a first input point for receiving the second output signal of the amplifier and a second input point for receiving the output of a constant current source. The current switching circuit switches current paths from the first and second input points to first and second output points in response switching control inputs. A first current mirror has an input point coupled to the second output point of the current switching circuit and an output point coupled to the first output signal of the amplifier circuit. A second current mirror has an input point coupled to the first output point of the current switching circuit, a first output point coupled to the output point of the first current mirror and a second output point coupled to an output terminal. A null-centered indicator is connected between a reference voltage terminal and the junction of the output point of the first current mirror and the first output point of the second current mirror. A potential difference detector can be inserted between the reference voltage terminal and the null-centered indicator.


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