The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 1980
Filed:
Jun. 16, 1978
Werner Egerbacher, Munich, DE;
Heinz Martin, Munich, DE;
Werner Mitzkus, Munich, DE;
Dieter Wunderlich, Geiselbullach, DE;
Siemens Aktiengesellschaft, Berlin and Munich, DE;
Abstract
Semiconductor component includes a closed housing having a base and a cover and being formed with a plurality of recesses therewithin, a plurality of semiconductor elements received in the recesses, respectively, and having at least two poles, a plurality of contact strips heat-conductively connected to and electrically insulated from the housing base, one of the poles of each of the semiconductor elements being in contact with a respective one of the contact strips and therethrough being in heat-conductive contact with the housing base, a plurality of supply electrodes, respectively, connected to another of the poles of the respective semiconductor elements, the respective contact strip in contact with a respective pole of one of the semiconductor elements and the respective supply electrode connected to a respective pole of another of the semiconductor elements being electrically connected to one another, a cross-piece disposed in the housing between the recesses wherein the semiconductor elements are received, and means secured to the crosspiece for yieldably biasing the supply electrodes against the semiconductor elements, the contact strips and the contact electrodes extending out of the housing and forming terminals for the respective semiconductor elements.