The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 1980
Filed:
Jun. 19, 1978
Theodore S Rzeszewski, Lombard, IL (US);
Paul D Frantzis, Chicago, IL (US);
Matsushita Electric Corporation, Franklin Park, IL (US);
Abstract
A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A first programmable frequency divider controlled by a reversible counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator, after passing through another programmable frequency divider, also is applied. The phase comparator output is a tuning voltage used to control the tuning of the local oscillator. A logic circuit responsive to characteristics of the received signals changes the count in the reversible binary counter to adjust the first programmable frequency divider to compensate for channel frequency offsets which may occur in excess of the pull-in range of the AFT discriminator circuit. To permit operation of the receiver as a signal seek receiver, a pair of signal seek push buttons for the 'up' and for the 'down' direction, respectively, are provided. Operation of either of these push buttons functions in conjunction with further logic circuitry and in conjunction with timing circuitry to automatically step tune the receiver channel-by-channel in the selected direction until a channel with a signal present is sensed by the first logic circuit, whereupon the signal seek circuit operation is disabled until one or the other of the signal seek push buttons is reactivated. The dwell time of the logic circuit for some steps is extended depending upon the relationship of the new channel to the previous channel. The dwell time also is extended for manual or direct access channel selection.