Cache arrangement for performing simultaneous read/write operations

Abstract

A cache system includes a storage unit organized into a plurality of levels, each including a number of multiword blocks and a corresponding number of address selection switches and address registers. Each address selection switch has a plurality of different positions connected to receive address signals from a plurality of address sources. A decoder circuit generates output signals for controlling the operation of the address selection switches. In response to previously defined level signals, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second position. An address specifying the location into which memory data is to be written is clocked into one address register while the address specifying the location from which an instruction is to be fetched is clocked into the remaining address registers. A comparator circuit compares signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. The comparator circuit generates signals which cause the delay of instruction access when there is a conflict between writing memory data and accessing instructions.