The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 1980
Filed:
May. 08, 1978
Fernando A Luiz, Monte Sereno, CA (US);
Harlan C Snyder, Saratoga, CA (US);
John H Sorg, Jr, Los Gatos, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and means for path independent reservation and reconnection of devices to CPU's operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (channels), each set coupling a corresponding CPU as a source node; a plurality of input/output devices; and a plurality of control nodes (control units), each node including means for accessing the devices, for selectively intercepting the paths in order to complete a signal path connection to a single destination device. Each control node further includes means (FIG. 2, element 25') for storing a table of independent path sets of CPU's and reserved devices and means (FIGS. 2-5) for managing the connection of CPU's to devices such that for any given selection, reservation or reconnection indication, the table is accessed by at least one control node for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved, if so, an available path is selected. The control nodes thus allocate dynamically dissimilar path sets to devices and CPU's on an allegiance basis in order to increase the signal path connection probability by the devices to counterpart CPU's involved in the reservation, release, or reconnection of the device and the CPU.