Timing circuit and method for a track following servo in a data storage

Abstract

A timing circuit for a track following servo system wherein an odd servo track having a series of prerecorded odd dibits thereon and an adjacent even servo track having a series of even dibits prerecorded thereon are moved with respect to a servo head to induce in the servo head signals that vary with the occurrence of the dibits and have an amplitude representative of the lateral position of the servo head with respect to the servo tracks. The servo head and its associated preamplifier produce a first signal having portions from both odd and even servo tracks and a second signal that is the inverse of the first signal. The first and second signals are processed by parallel identical circuit paths to generate a clocking signal that times the remainder of the data storage system in synchronism with the spacing of dibits on the servo tracks. Each of the parallel identical circuit paths includes a circuit for discriminating between true dibits and spurious noise signals on the servo tracks, a counter circuit for passing only those dibit pulses that occur within a given time interval after the next preceding dibit, and a circuit for producing a timing pulse at a specified time after the preceding pulse to maintain system synchronization even in the absence of a dibit on one of the tracks.