Addressing circuitry for a vertical scan dot matrix display apparatus

Abstract

An addressing circuitry for a dot matrix vertical scan plasma display includes a character row counter and a character column counter, a random access memory, a dot pattern generator, a parallel to series shift register, and a driver for the display. The addressing circuitry is responsive to a processor. Alpha-numeric digital characters to be displayed are read out of the memory in sequence in response to a sequence signal from the character row counter and the character column signal output. The words read out of the memory are converted into dot matrix pattern by the dot pattern generator and displayed on the plasma display via the parallel to serial shift register and driver. An offset adder is used when the number of character rows and the number of characters per row of the display are other than binary progression numbers in generating a sequence signal. The offset adder is interposed between the random access memory and the row and column outputs. The offset adder is of a design that eliminates the wasted character memory locations that would otherwise take place in its absence. The addressing circuitry includes control logic responsive to the processor unit and the random access memory for enabling the dot pattern generator to apply cursor, blinking or blanking control signals selectively to the display.