Microprogrammable computer utilizing concurrently operating processors

Abstract

A microprogrammable CPU for a computer utilizes an architecture wherein macro instructions of the computer repertoire are executed by micro instruction routines stored in a control store memory. The micro instruction routines are comprised of micro instruction words for controlling the micro operations to be performed in executing the macro instructions. The CPU includes a plurality of local processors each configured to perform a plurality of the micro operations. A macro instruction fetched into the macro instruction register of the computer addresses the corresponding micro instruction routine in the control store memory and the plurality of local processors operate concurrently to simultaneously perform the micro instructions of the routine on behalf of the fetched macro instruction. Thus a stream of macro instructions flowing through the macro instruction register is decomposed into a plurality of concurrently executed micro instruction streams flowing through the respective local processors. Preferably the local processors are constructed utilizing micro processor LSI integrated circuits. Each local processor is operated in an overlapped mode with respect to micro instruction fetching, execution and storage of results. Each local processor has real and phantom branching capabilities provided by plural next address fields and plural function control fields in the micro instruction words. Decision points provided in the computer select between the next address fields and select between the function control fields to perform the real and phantom branching respectively. The decision points are provided by control logic driven by tables storing functions of plural variables where functions and variables are selectable by the micro instruction words.