Integrated circuit method

Abstract

A method for fabricating self-aligned, walled emitter, oxide isolated integrated circuits. A layer of oxidation resistant material is formed on an oxide isolated epitaxial layer on a silicon substrate. A pattern of apertures is opened in the oxidation resistant layer to expose portions of the epitaxial layer. The apertures extend across the oxide isolated silicon material and define the spaces between the contacts of the active devices of the circuit. Dopant impurities are applied through these apertures to form an inactive base region. The substrate is heated in an oxidizing ambient to form a relatively thick oxide on a portion of the epitaxial layer exposed through the apertures. The oxidation resistant layer is again selectively etched to expose those portions of the epitaxial layer where the active device regions are to be formed. In this step a single mask is used to open a plurality of device regions. The mask is used in conjunction with the oxide isolation and the relatively thick oxide to precisely define the spacing between these regions. Dopant impurities are applied through selected openings to form the active base region. Opposite type dopant impurities are applied through the same openings to form the emitter regions. Dopant impurities are also applied through further selected openings to form base contact areas and collector contact areas. The integrated circuit device thus formed has a base and emitter structure which is bounded on its edges by the isolation oxide or by the relatively thick oxide.