Processor overload arrangement in time division multiplex exchanges

Abstract

This invention is concerned with a processor-overload relief facility in a time division multiplex (t.d.m.) processor-controlled exchanges. Under overload conditions rejection of new calls may be required until this condition is relieved and this proposal is to meet the relief function by peripheral hardware while retaining the ability to process emergency (999) calls during overload. An incoming signalling unit which is responsive to incoming seize, dialling and other signals, is provided with multi-bit stores on a one per channel basis; each such store interfacing with processor on a read/write basis. Normally the signalling unit responds to any incoming channel-seized condition and sets the `seize` bit (S) in the appropriate channel store which reports seizure to the processor. Dialled pulses are detected and accumulated in the store, and each complete digit is transferred to the processor for call control purposes. During overload conditions a common control circuit inhibits (except in the case of channel stores already receiving an S signal) certain normal transfer paths between the signalling unit and channel stores but a transfer path is left open if a 999 call is received on a level 9 circuit of the exchange, so that a new seize signal can be diverted to another storage location whereupon a '999 signal with channel identity' is transmitted to the processor.