Circuit indicating phase relationship

Abstract

There is disclosed a circuit for providing a comparison signal representing phase relationship between a clock pulse train and a variable rate input pulse train. The comparison signal can be used to synchronize clock and input pulse trains. The circuit includes a phase difference measuring circuit providing a first signal proportional to phase difference between input pulse train and clock pulse train, the signal having related discontinuities at the points of minimum and maximum phase difference between input and clock pulse trains. A second signal is generated representing a selected value of phase difference, the selected value being greater than the minimum phase difference and less than the maximum phase difference. First and second signals are then compared to provide a signal representing difference between the measured and selected values of phase difference. The comparison signal thereby avoids the discontinuities at minimum and maximum values of phase difference by representing phase relationship between input and clock pulse trains relative to the selected value of phase difference rather than to the maximum or minimum values. In a preferred embodiment, decoding circuitry decodes an input pulse train in self-clocking code to provide data output in binary code.