Bit error detecting circuit for use in a digital signal transmission line

Abstract

A bit error detecting circuit for a digital signal transmission line of the type having a main decision circuit and a sub-decision circuit is disclosed. The purpose of the sub-decision circuit is to provide a prediction of a fault in the transmission, and this is accomplished without being adversely effected by a drift in the threshold level. A clock recovery circuit is responsive to the input digital signal to produce a clock signal which is supplied to both the main decision circuit and the sub-decision circuit and to a pattern generating circuit such as a binary counter. The main decision circuit decides the binary code of the input digital signal with respect to a first reference level. The binary code pattern from the pattern generating circuit is added to the input digital signal and the sum supplied to the sub-decision circuit which decides the binary code of the sum with respect to a second reference level. The outputs of the main decision circuit and sub-decision circuit are applied to an Exclusive OR circuit to provide a monitor output signal.