The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 1980
Filed:
May. 20, 1977
Ruediger Mueller, Munich, DE;
Siemens Aktiengesellschaft, Berlin & Munich, DE;
Abstract
A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other conductivity type is located in the epitaxial layer in a plane spaced below the outer surface of said epitaxial layer and lying substantially parallel thereto. A load transistor and an output transistor are formed by constructing the arrangement so that the buried layer provides the base of the load transistor and the emitter of the output transistor. The emitter of the load transistor is provided by a portion of the epitaxial layer which lies below the deep-implanted doped zone. The collector of the load transistor and the base of the output transistor are provided by the portion of the epitaxial layer which lies above the deep-implanted zone. A Schottky electrode on the outer surface of the epitaxial layer provides the collector of the output transistor. A plurality of Schottky diodes are also formed in a portion of the epitaxial layer which possess a lower Schottky barrier than the Schottky electrode of the output transistor.