Process for minimum overlap silicon gate devices

Abstract

A method of manufacturing a silicon gate MIS device providing automatic formation and alignment of the gate structure during formation of adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents-- typically oxide and silicon-- are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to a predetermined size beneath the overhanging mask. A deposition mask in the form of the photoresist mask or the gate silicon oxide and which is of the same size as the photoresist mask, is used to control the deposition of impurities within predetermined surface areas of the substrate which are spaced a predetermined distance from the silicon gate boundaries. By diffusion, the impurities are driven into the substrate to the desired depth to complete the source and drain, which are thereby driven laterally into coincidence with the gate boundaries. The aligned, non-overlapping relationship of the gate structure with the source and drain minimizes gate overlap capacitance.