Method for manufacturing a semiconductor integrated circuit device

Abstract

In manufacturing an insulated gate field effect transistor integrated circuit using both a self-alignment diffusion process and a non-self-alignment diffusion process, a mask is formed having a combined pattern of areas at which a subsequent self-alignment diffusion and a non-self-alignment diffusion will occur. An oxidation prevention layer for preventing thermal oxidation of a substrate is selectively formed on a semiconductor substrate using the prepared mask. Those areas of the semiconductor substrate which are not covered by the oxidation prevention layer are oxidized by thermal oxidation to form oxidized layers thereon, and impurities are diffused first in the areas of the substrate corresponding to the non-self-alignment portion of the mask pattern and subsequently in the areas of the substrate corresponding to the self-alignment portions of the mask pattern to build in an insulated gate field effect transistor network. According to the present method, the height of stepped areas produced in the insulating layer on the semiconductor substrate are minimized so that the breakage of the metallized pattern which extends over the stepped areas is prevented.