Buffer storage and control

Abstract

A re-entrant shift register comprising eight levels and in the illustrative embodiment eight stages per level, is selectively used in the buffering of information between an asynchronous signal source, e.g., a manual keyboard and a data sink, e.g., a controller which accepts information upon an asynchronous basis. Information to be transmitted from a data source to the data sink is entered in parallel in a register in the form of a latch under control of write control circuitry. Similarly, data to be transmitted to the asynchronous data sink is temporarily stored in a parallel output register in the form of a latch. The writing of information into and out of the output latch is under the control of read control circuitry. The write control circuit includes a write counter and the read control circuit includes a read counter. These counters are advanced by a common clock signal which is further utilized in the gating of information within the write control and read control circuits and in the control of the shift register. The shift register and the attendant input and output circuitry is arranged such that an information word can be selectively routed directly between the input latch and the output latch to eliminate the delay incurred in traversing the shift register whenever the input and output data rates are such that buffering is not required. Additionally, where the input information indicates that an input data word is being repeated, the information is gated directly from the input latch to the output latch independently of the rate at which the input signals occur.