Junction field effect transistor for use in integrated circuits

Abstract

A junction field effect transistor is incorporated into a conventional monolithic bipolar integrated circuit using compatible processing steps. The transistor source and drain regions are produced during IC base diffusion and the gate contact during IC emitter diffusion. A channel is ion implanted in the region between source and drain. A second, shallower, opposite conductivity ion implant is applied over the channel so as to overlap and cover. Thus, a subsurface channel is created. A third ion implant of slightly deeper character and to a much heavier dosage is created in the region between and separated from the source and drain using an impurity of the same conductivity type as the second ion implant. This third ion implant is designed to span the channel without contacting either the source or drain, thus creating a top gate ohmically connected to the bottom gate.