The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 1979
Filed:
May. 24, 1978
Hiroshi Tamura, Yokohama, JP;
Masao Kato, Ichikawa, JP;
Yukuya Tokumaru, Yokohama, JP;
Masanori Nakai, Yokohama, JP;
Abstract
A measuring apparatus comprises: a first series circuit having first and second resistors connected between a power source terminal and ground; a second series circuit having a thermistor and a third resistor connected between the power source and ground; a first variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the first and second resistors of the first series circuit; a second variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the thermistor and the third resistor; a first counter which counts the pulse signal from the second variable frequency oscillator to produce a high level signal till it counts a given number of pulses; and AND gate connected to the output terminal of the first variable frequency oscillator and the first counter, a second counter for counting the pulse fed from the first variable frequency oscillator via the AND gate; and a display circuit for displaying the contents of the counter. The first and second variable oscillating circuits each have an odd number of inverters which are cascade-connected and each formed of an integrated injection logic circuit with a power receiving terminal connected to the first or second series circuit, the output terminal of the last stage inverter being connected to the input terminal of the first stage inverter.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile