The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 1979
Filed:
Sep. 17, 1976
Roland J Handy, Northridge, CA (US);
Thomas A Zimmerman, Palos Verdes Peninsula, CA (US);
TRW Inc., Redondo Beach, CA (US);
Abstract
A logic gate utilizing charge transfer structures is disclosed which forms the building block for a TWO (2)-INPUT ADDER (HALF ADDER) and a THREE (3)-INPUT ADDER (FULL ADDER). The logic gate includes a first storage gate for receiving charge packets representing binary digital input signals. The storage gate couples in a first path to a first transfer gate which allows the storage gate to store only one unit quantity Q of charge and to transfer any excess quantity of charge to a master gate. The master gate is connected to a slave gate which causes the latter to operate as a barrier gate when the master gate contains a unit quantity Q of charge or to operate as a transfer gate when the master gate contains no charge. A control gate couples the first storage gate in a second path to the slave gate. The control gate exercises control over the transfer of charge in the second path until such time as the master gate can receive and store the excess charge from the first storage gate and thereby determine the appropriate state of the slave gate before the second path is allowed to transfer charge from the first storage gate.