Virtual address translation speed up technique

Abstract

Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a virtual address register. A field of bits within the virtual address are presented simultaneously as an address to a translation table and a pre-translation table where the pre-translation table has two entries per row and each entry contains some of the virtual address bits of corresponding candidates in the translation table. The pre-translation table is quite narrow compared to the translation table and is preferably, but not necessarily, implemented in latches or as a very fast array compared to the translation table. The selected entries from the pre-translation table are compared with corresponding bits from the virtual address register and the results of the precompare generate an address bit which together with the other address bits select the candidate from the translation table which is more likely to compare with a larger group of address bits from the virtual address register. In the event both entries from the pre-translation table compare with the corresponding bits from the virtual address register and the selected candidate from the translation table does not compare with the larger group of address bits from the virtual address register, the address bit from the precompare is forced to an opposite state whereby the other candidate is selected.