Synchronization control system for firmware access of high data rate

Abstract

In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory. When the input register of the FIFO buffer is filled during a data transfer from main memory to the disk device, or when the FIFO buffer is empty during a transfer of data from the disk device to main memory, hardware controlled data transfers are not required. In that event the firmware control system is permitted to access the common bus to service unsolicited bus requests.