The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 1979

Filed:

Jan. 11, 1977
Applicant:
Inventors:

Sanford Lebow, Westlake Village, CA (US);

Daniel Nogavich, Newbury Park, CA (US);

Eugene Nogavich, Thousand Oaks, CA (US);

Assignee:

Pactel Corporation, Newbury Park, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
156632 ; 156631 ; 156645 ; 156902 ; 156153 ; 156233 ; 156249 ; 156289 ; 204 15 ; 204 23 ; 204 / ; 204 / ; 427 96 ; 427264 ; 427282 ; 427409 ;
Abstract

The method of manufacturing printed circuitry with sufficiently high resolution to permit line densities of at least 1 mil lines on 3 mil centers includes the steps of placing a thickness of dry film photoresist on a smooth, polished substrate or carrier optionally, applying a thin lubricating layer of spray wax to the exposed surface of the photoresist, wringing a mask defining a desired conductive circuit pattern into high integrity, intimate contact with the surface of the resist, exposing and developing the resist to remove the resist from the smooth surface in regions where the conductive circuit pattern is to be formed, electroplating the conductors within the voids formed in the resist; removing all remaining resist, laminating a flowable dielectric material to the smooth surface of the substrate and the conductive circuit pattern, and removing the laminate material and conductive circuit pattern from the smooth surface. If desired, conductive via interconnects can be selectively formed and additional layers of circuit patterns can be formed atop the first high resolution layer.


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