Method of fabricating an mnos memory device

Abstract

A method for fabricating a variable threshold IGFET free of parasitic effects and the 'floating gate' effect. The method comprises forming a semi-conductive substrate of a first conductivity type material, forming a pair of laterally spaced diffusion regions of opposite conductivity type to the substrate material adjacent one surface of the substrate and forming a variable thickness oxide layer having a portion of minimum thickness with a predetermined width at least partially overlying the interstitial portion of the substrate, a portion of intermediate thickness substantially greater than the minimum thickness and partially overlying the interstitial substrate portion and at least one of the pair of spaced diffusion regions, and a remaining portion of maximum thickness substantially greater than the intermediate thickness. A layer of silicon nitride dielectric material is deposited to a predetermined thickness on the oxide layer, after which an electrically conductive electrode is formed on the dielectric layer in the region overlying the minimum thickness portion of the oxide layer to a width less than the width of the minimum thickness portion of the oxide layer. The IGFET is completed by forming ohmic contacts with the diffusion regions. The width of the oxide layer portion of minimum thickness is no less than the width of the gate electrode plus the minimum achievable alignment tolerance length over the width of the gate electrode, while the width of the oxide layer portion of intermediate thickness is no greater than the width of gate electrode less the same alignment tolerance.