Mos ram cell having improved refresh time

Abstract

In a microelectronic, metal-oxide-semiconductor dynamic random access memory cell having an MOS capacitance signal storage region, leakage current has been found to have a critical dependence upon the voltage level at which the storage gate is operated (V.sub.STORE). The leakage rate undergoes a sharp transition to a low state below a certain critical V.sub.STORE. This transition is due to the shutting off of the leakage from the periphery and field region around the cell. Consequently, maximum refresh time is achieved by modifying the cell to permit operation of the storage gate below the critical voltage, which may be at or near ground level. For an n-channel cell, permanently shifting the flatband voltage at the silicon-oxide interface of the storage capacitor in the negative direction can generate a potential well for charge storage with a very small V.sub.STORE. Preferably, this flatband voltage shift is achieved by a shallow implant of a donor impurity in the silicon surface of the storage region of an n-channel device, or an acceptor impurity for a p-channel device. The critical maximum V.sub.STORE is a function of the channel-stop doping level. Increasing the channel-stop doping level results in a higher critical V.sub.STORE without a significant increase in leakage; however, since circuit speed and breakdown voltage are reduced by increased channel-stop doping, such an alternative option cannot fully offset the need for a shift in the flatband voltage, so that the low leakage condition is achieved by a combination of increased channel-stop doping and shifted flatband to permit lower V.sub.STORE.