Impedance trim network for use in integrated circuit applications

Abstract

An adjustable impedance network is disclosed which is suitable to be used in monolithic circuit applications to eliminate problems caused by processing tolerances. One example of such use is to employ the impedance network in the collector circuit of a differential amplifier to eliminate input voltage offset errors. The impedance network includes a plurality of impedance elements serially coupled together between first and second terminals which in the above example would be coupled to respective collector output electrodes of the differential amplifier. Each impedance element is initially electrically shorted by a respective one of a plurality of thermally machinable metallic link. In addition, a selected number of the impedance elements are electrically shorted to a common terminal by two additional metal links which are serially connected together across said selected number of impedance elements. The impedance elements are binary weighted to provide a maximum number of trim values. A laser apparatus may be used to cut or machine appropriate links to open circuit the link to add predetermined resistance between either the first or second terminal of the network and the common terminal thereof. Thus, in the above example, resistance may be added to either collector load resistor of the differential amplifier to compensate for mismatch in the transistors comprising the amplifier.