The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 1979
Filed:
Aug. 26, 1977
James A Stewart, Menlo Park, CA (US);
GTE Automatic Electric Laboratories, Inc., Northlake, IL (US);
Abstract
In a carrier subscriber terminal, a voltage regulator converts the line voltage to a relatively uniform operating voltage for driving a power converter that charges a local battery. The control circuit for the converter comprises a programmable unijunction transistor (PUT) Q1 having a gate and anode connected to intermediate points of associated pairs of resistors R1-R2 and R3-R4 that are electrically connected across the line, and having a cathode connected through a first capacitor C1 and associated discharge path to one side of the line. A Zener diode D5 is resistively connected across the line to establish a reference voltage which is connected through a first diode D1 to the PUT anode, through second and third diodes D2 and D3 to the PUT gate, and through only the second diode D2 to a second capacitor C2 of the regulator. During normal operation, the diodes conduct to connect the reference voltage to the PUT gate and anode to bias the PUT off so that the second capacitor C2 is charged to the Zener-reference voltage. A constant high or increasing line voltage which is greater than a first prescribed value and a constant low or decreasing line voltage which is less than a second prescribed value cut off only the first and third diodes D1 and D3, respectively, to enable the PUT to conduct to dump the charge on the second capacitor C2 into the first capacitor C1 which discharges slowly, when the PUT is again nonconducting after C2 is discharged, to hold the converter off for a long time interval.