Method for making narrow channel fet by masking and ion-implantation

Abstract

A method for making an FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. This FET is fabricated by (1) forming on the field oxide a photoresist mask having a relatively narrow aperture; (2) overetching the field oxide beneath the photoresist mask aperture to form a relatively wide aperture in the field oxide, leaving a photoresist overhang; (3) implanting the substrate through the relatively narrow photoresist mask aperture to provide an enhancement section of the channel region; (4) removing the photoresist mask; and (5) depletion implanting the substrate through the relatively wide field oxide aperture. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET. The effective channel width of the depletion FET approximates the combined width of the two narrow depletion regions and is controlled by the photoresist overhang, i.e., by the relative width dimensions of the two mask apertures. The method is applicable to both silicon and metal gate technology, to n-channel and p-channel, and to various combinations of enhancement and/or depletion devices.