The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 1979

Filed:

Jul. 07, 1977
Applicant:
Inventors:

Nozomu Harada, Yokohama, JP;

Nobuhisa Kubota, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; B05D / ;
U.S. Cl.
CPC ...
427 85 ; 148174 ; 148187 ; 148188 ; 148191 ; 4272 / ; 4272 / ; 427399 ;
Abstract

A manufacturing method of semiconductor device having a single layer or multilayer of polycrystalline semiconductor including doped impurity is provided which comprises a step of forming a first polycrystalline semiconductor layer with doped impurity on a semiconductor substrate and another step of forming a second polycrystalline semiconductor layer without doped impurity on the first polycrystalline semiconductor layer. The manufacturing method of the invention provides excellent MOS FET's in the semiconductor device of which the threshold voltage varies little. High reliable semiconductor device may further be manufactured with a high yield.


Find Patent Forward Citations

Harada, Nozomu. (1979). Manufacturing method of semiconductor devices (U.S. Patent No. 4143178). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4143178

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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