Isolation of integrated circuits utilizing selective etching and

Abstract

Disclosed is a method of isolating portions of integrated circuits which permits closely packed structures. A semiconductor wafer is provided with a substrate of one conductivity type, a first layer of opposite conductivity type and high impurity concentration formed thereon, and a second layer of either conductivity type but lower concentration formed over the first layer. The major surfaces of the semiconductor layers are parallel to the (110) plane. Narrow grooves with sidewalls in the (111) plane are etched into the first layer. A shallow diffusion of impurities of the same conductivity type as the first layer is performed in the sidewalls and bottom of the grooves which permits the first layer to be contacted from the surface of the second layer. The groove is then etched further until it extends into the underlying substrate. Impurities of the same conductivity type as the substrate are diffused into the bottom and sidewalls of the grooves. The concentration of these impurities is chosen so that a chanstop region is formed in the substrate without appreciably affecting electrical conductivity between the first layer and the regions formed by the previous diffusion.