The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 1979
Filed:
Jun. 23, 1976
Kinya Takamizawa, Yokohama, JP;
Kazuhiro Iinuma, Yokohama, JP;
Tokyo Shibaura Electric Co., Ltd., Kawasaki, JP;
Abstract
An ultrasonic wave transmitting and receiving apparatus comprises a plurality of electrical-acoustic converting elements arranged in the same plane; a clock pulse generator; a plurality of first switching circuits coupled between the clock pulse generator and each of the electrical-acoustic converting elements; a data signal receiving circuit; a plurality of second switching circuits coupled between the data signal receiving circuit and each of the electrical-acoustic converting elements; a first control circuit adapted to control the first switching circuit so as to radiate a beam of ultrasonic wave from the electrical-acoustic converring element into a to-be-measured subject by sequentially supplying the clock pulse of the clock pulse generator; and to control the second switching circuit so as to sequentially supply to the data signal receiving circuit an electric signal generated from the electrical-acoustic converring element which receives a beam of ultrasonic wave reflected from the subject; three memories coupled to the data signal receiving circuit; a second control circuit adapted to control the memories so as to sequentially write at a predetermined rate data signals from the data signal receiving circuit into the memories and, when the data signal is being written into one of the memories, read data at a rate higher than the predetermined rate from the remaining memories; and an addition circuit adapted to add together the readout data signal from the memories so as to deliver an output.