Watch dog timer module for a controller

Abstract

A controller for directing a host machine which is operative to include a central processor for program execution, a system bus controlled by the central processor for carrying data, address and control signals, and a data memory coupled to the system bus. Additionally included is a direct memory access moudle for conveyance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon acknowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update. Operative to interface with the above is a fault timer including a counter clocked at a given frequency for reset by the state signal from the direct memory access module if within a given period, and upon absence of reset for generating a fault signal, and a bistable unit operative to receive the fault signal from the counter for clocked latching thereof, and for generating a hold signal through the direct memory access module to the central processor and a disabling signal to the host machine.