The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 1978
Filed:
Jan. 10, 1977
Kenneth Gillett, Redondo Beach, CA (US);
Edward L Steiner, Macedon, NY (US);
Kenton W Fiske, Fairport, NY (US);
Kenneth A Davis, Honeoye Falls, NY (US);
William P Kukucka, Webster, NY (US);
Thomas Criswell, Venice, CA (US);
Philip Richardson, Pacific Palisades, CA (US);
Xerox Corporation, Stamford, CT (US);
Abstract
A non-volatile storage module as utilized in a controller for directing a plurality of control registers of a host machine. The controller includes a central processor that is communicatively coupled through a system bus having control data, and address lines to the module and host machine. The non-volatile storage module includes a data memory operative to interface with the system bus for storing data, and for input-output of the data therefrom through the system bus upon command of the central processor. In addition, the module further includes a power storage unit coupled to the data memory for distributing a plurality of power signals from the host machine through a plurality of critical and non-critical power lines to the data memory for providing a power source that may be utilized therein for a power down condition and for sensing a power down condition on the critical power line from the power storage unit for the switching thereof to the data memory. The module also includes an apparatus that is operative upon indication of a power down condition from the host machine for generating an enabling signal to the data memory while a current address signal on the system bus is being received by the data memory.