Phase locked loop for providing continuous clock phase correction

Abstract

A phase locked loop apparatus for providing a continuous output digital clock signal having first and second states which is continuously phase locked to a reference digital data signal, which digital data signal comprises at least one data transition, utilizes every data transition to continuously correct the clock phase. For pseudo video scan lines, such as utilized for row grabbing, when such scan lines contain a start bit, the phase locked loop makes a single correction each empty or non-data line utilizing the start bit to insure that phase lock exists at the beginning of the first non-empty or digital data containing scan line. The phase locked loop contains a voltage controlled oscillator operating in conjunction with a flip-flop functioning as a phase detector, with the state of the flip-flop being dependent on the phase condition between the digital data signal and the digital clock signal.