Volatile/non-volatile logic latch circuit

Abstract

There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such, it acts as an ordinary volatile semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. Non-volatile storage capability is achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state. Therefore, if power is removed and then returned, the latch will always settle into a state dictated by the final state that existed in the latch before the high voltage pulse was applied. In this way the variable threshold elements of the latch cell make it a non-volatile memory element. Fixed threshold IGFETs, connected so as to bypass the variable threshold elements, enable the latch cell to continue to operate even after a variable threshold element has been rendered irreversibly non-conductive by a high voltage pulse.