The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 1978
Filed:
May. 04, 1977
Adrian R Hartman, Westfield, NJ (US);
Hans Melchior, Pfaffhausen, CH;
David P Schinke, Berkeley Heights, NJ (US);
Richard G Smith, Basking Ridge, NJ (US);
Bell Telephone Laboratories, Incorporated, Murray Hill, NJ (US);
Abstract
Described is a method of fabricating front-illuminated silicon photodiodes having high quantum efficiency, a short response time, (high gain and low excess noise in the case of avalanche diodes), low dark currents and good reliability. In the fabrication of an n.sup.+ -p-.pi.-p.sup.+ APD the method includes the steps of: (1) epitaxially growing a high resistivity .pi.-type silicon layer on a high conductivity p-type silicon substrate; (2) forming an n-type guard ring in the .pi.-layer; (3) forming a p-type channel stop around the guard ring; (4) forming in the .pi.-layer a p-layer by ion implantation and by driving in the implanted ions by heating in a suitable atmosphere; (5) masking the p-layer and introducing phosphorus into the backside to getter defects and/or impurities; (6) ramping the furnace temperature during steps (2) through (5) to reduce crystalline defects; (7) forming a thin n.sup.+ -layer in the p-layer; (8) forming an anti-reflection and passivation coating on the n.sup.+ -layer; and (9) forming electrical contacts to the substrate, the guard ring and the channel stop so that the latter two contacts overlap the surface portions of the corresponding metallurgical junctions. The n.sup.+ -layer is made extremely thin in order to reduce hole injection caused by light incident on that layer, and the ion implantation-drive step (4) and subsequent steps which involve heating are mutually adapted so that the resultant electric field profile in the multiplication region (p-layer) is substantially triangular. A similar process, which omits step (4), is also described for the fabrication of n.sup.+ -.pi.-p.sup.+ photodiodes.