Method of passivating high-voltage power semiconductor devices

Abstract

Several junction-type semiconductor chips, specifically NPN transistors, are simultaneously produced by mesa technique from a semiconductor wafer by adhering to one major surface thereo a supporting structure including a bonding layer of wax, similarly adhering a protective layer of a relatively soft material -- likewise a wax -- to the opposite major wafer surface, and dividing the wafer into chips temporarily held together by the supporting structure. The last-mentioned step involves a splitting of the protective layer into isolated sections by making incisions in that layer cutting into the underlying wafer body, followed by an erosion of the semiconductor material of that body by an etching solution to form channels which extend completely across the wafer and terminate at the supporting structure, these channels being widened in the immediate vicinity of the protective layer to form undercuts. A continuous passivating film is applied, e.g. by vapor deposition, to the channel walls and to the several isolated sections of the protective wax layer adhering to the exposed chip faces, the film enveloping projecting edge portions of these sections which extend partly across the channel entrances. After these edge portions are mechanically cut off, film segments adhering to the isolated wax-layer sections can be removed by dissolving the wax; concurrent dissolution of the bonding layer of the supporting structure removes that structure from the chips which then remain interconnected only by parts of the passivating film bridging the lateral channel walls.