Digital speed detecting circuit for a rotating member having a wide

Abstract

A digital speed detecting circuit of the type in which pulses of a clock frequency are counted during a time interval of a cycle of the sinusoidal signal obtained from a sensor of the rotating member whose speed is being measured. The pulse count throughout the speed range of the rotating member is adjusted to be within a range best suited for accurate evaluation, since the pulse count exceeds this range at high and low speeds. This is accomplished in a first embodiment by shifting to a different counting frequency in different speed ranges and correcting the speed signal obtained by a factor corresponding to the degree of frequency change. In a second embodiment, the counting frequency is monitored and adjusted each cycle of the sinusoidal signal by comparing in a shift register the stage of advancement of a binary counter that produces the pulse count with a reference stage establishing the upper limit of the evaluation range. The frequency adjustment required each cycle depends upon the speed range of the rotating member and is monitored to provide a correction factor by which the speed signal is adjusted in accordance with the time required to shift the most significant bit of the shift register signal to the reference stage. In the third embodiment, the time interval of the sinusoidal sensor signal is increased in binary steps associated with different speed ranges of the rotating member so that the pulse count is registered during each speed range for various durations.