Integrated circuit process utilizing lift-off techniques

Abstract

A method for making high density integrated circuits which utilizes lift-off techniques provides a structure having a single layer of insulating material for both the dielectric of a storage capacitor and the insulator for a gate or control electrode of a switching element. The steps of the method include forming a thin layer of silicon dioxide on a silicon substrate followed by a layer of first doped polysilicon and, optionally, a layer of silicon nitride and then a layer of photoresist. The layers are etched to the silicon dioxide surface with the exception of the portion of the layers overlying a region defined as the gate or control electrode of the switching element. A second layer of doped polysilicon is then deposited over the remaining structure to provide on the silicon dioxide layer a second conductive layer adjacent to but spaced from the first polysilicon layer forming the gate or control electrode. The silicon nitride, when used, is etched away and a strip of conductive metal is placed in contact with the first conductive polysilicon layer after the second doped polysilicon layer has been appropriately oxidized to form an insulating medium over this second polysilicon layer and between the first and second polysilicon layers. Any desired n+ regions may be formed in the silicon substrate by diffusing impurities into the substrate prior to forming the silicon dioxide layer, or the n+ regions may be formed after the silicon dioxide has been formed by using appropriate ion implantation techniques. By employing this method, high density one device memory arrays may be produced by using the first doped polysilicon layer for forming the gate electrode of a field effect transistor and the second doped polysilicon layer as an electrode of the storage capacitor.