The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1978
Filed:
Apr. 04, 1977
Applicant:
Inventor:
Frank J Swiatowiec, Tempe, AZ (US);
Assignee:
Motorola, Inc., Schaumburg, IL (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364787 ; 364760 ;
Abstract
A high speed multiplier array implemented with a current switch emitter follower logic gate employs an inverted carry signal internal to the array. External carry signals received by the array are first inverted for internal processing. This implementation eliminates the necessity of employing a buffer gate between subarray integrated circuit chips or cells and thus decreases propagation delays in the overall array.
Quick Actions:
Swiatowiec, Frank. (1978). Emitter coupled multiplier array (U.S. Patent No. 4122527). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4122527
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile