The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1978
Filed:
Jul. 29, 1977
Applicant:
Inventors:
Kenji Kawagai, Kawasaki, JP;
Shigeki Yoshida, Kawasaki, JP;
Assignee:
Tokyo Shibaura Electric Company, Limited, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307205 ; 307214 ; 307215 ; 307218 ; 307251 ; 307270 ;
Abstract
A logic circuit using CMOS transistors, in which electrical power is supplied to a CMOS logic circuit that is formed of P-channel type and N-channel type MOS transistors by way of a depletion type MOS transistor. The output level with respect to the voltage of the power source that is used is set at some point by the design of the depletion-type MOS transistor.
Quick Actions:
Kawagai, Kenji. (1978). Logic circuit using cmos transistors (U.S. Patent No. 4122360). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4122360
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile