The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 1978
Filed:
Apr. 20, 1977
Andrew G Varadi, Saratoga, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
This disclosure relates to an MOS or FET memory array that uses a single voltage source (i.e., 5 volts) and operates basically as a static memory array rather than as a dynamic memory array that requires the gates of the MOS devices of the memory array to be periodically refreshed to restore or refresh the memory states contained therein. Each of the memory cells of the memory array contains four MOS devices that are cross-coupled into a flip-flop type of memory cell. All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device. The large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array. The resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states ('1' or '0') in each of the memory cells.