Circuit for testing transistors or the like

Abstract

The circuit includes sources of periodic, low duty cycle, load terminal energizing and control terminal driving pulse waveforms. During each cycle, the waveforms occur only during successive test intervals occupying only a small portion of each cycle. During each test interval a load terminal energizing pulse is generated to energize a transistor or FET device of a different conductivity type and a control terminal drive voltage is penetrated which initially is of a polarity which would render a transistor or FET device of the associated conductivity type non-conductive, and then switches to a voltage of opposite polarity to render such device fully conductive. There is provided means for selectively varying the control terminal driving current which flows in an operating device from a relatively high to a relatively low level. Signals are derived showing the transition in the conductive states of the devices under test during the polarity transition of the control terminal drive voltage waveform. A first detecting and storage circuit is provided which detects and stores the occurrence of a current transition during the first test interval showing a possibly properly operating device of one conductivity type, and a second detecting and storage circuit is provided which detects and stores the occurrences of a current transition during the second test interval showing a possibly properly operating device of the opposite conductivity type. The storage circuit sets a leakage and material type test voltage producing circuit to produce a test voltage of proper polarity, depending upon whether the possibly properly operating device is of one or the other conductivity type.