Plural load power controller with time-shared processor

Abstract

A power controller arrangement employs a digital processor to monitor and control plural loads, e.g., to monitor and maintain at prescribed levels the temperatures of plural missiles. During each load data processing cycle of operation, the processor presets a down-counter which governs load (e.g., missile heater) energizing power by duty factor modulation. The value preset into the counter is dependent upon any measured temperature error, and the then obtaining load power level. In accordance with one aspect of the present invention, the modulation governing counter is periodically decrimented to progressively reduce power delivered to a load absent sufficiently frequent processor updating of the load-associated regulating circuitry. This provides fail-safe load passivation upon processor failure or overload.