The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 1978

Filed:

May. 31, 1977
Applicant:
Inventor:

Tetsuo Yamaguchi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307209 ; 307261 ; 307269 ; 328 62 ;
Abstract

An integrated circuit includes an input terminal to which a '1,' 'float' and '0' level input signals are selectively supplied; a clock pulse generator for generating a second clock pulse during the high level period of a first clock pulse and a third clock pulse during the low level period of the first clock pulse, and first and second latch circuits operated in response to the second and third clock pulses, respectively, of the clock pulse generator. The input terminal is connected through a resistor to the output of the first clock pulse. The input terminal is also connected to the inputs of the first and second latch circuits. The integrated circuit generates three kinds of outputs whose logical states correspond to different levels of three input signals, respectively, which are selectively supplied to said input terminal.


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