Random digital code generator

Abstract

The specification discloses a random digital code generator operable over a series of key cycles for generating a randomized digital bit during each key cycle. The generator includes a plurality of first registers each having a predetermined cycle period which does not have a common factor with the cycle period of any other of the first registers. Circuitry is provided to step each of the first registers a predetermined number of steps per key cycle. A plurality of second registers are provided, along with circuitry for generating different numbers of clocking signals per key cycle for each of the second registers. Circuitry generates control pulses in response to the clocking signals and further in response to digital bits derived from selected taps on the first registers. The control pulses randomly control the number of times each of the second registers is stepped during each key cycle. The number of steps taken by each of the second registers does not have any common factor with the number of steps taken by any of the other second registers. Circuitry is responsive to the outputs of the second registers in order to generate a randomized digital bit during each key cycle. This circuitry includes two levels of multiplexing and further includes bit flipping and spoof circuitry to enhance the security and randomness of the generator.