The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1978

Filed:

May. 27, 1977
Applicant:
Inventors:

Kenshi Manabe, Yokohama, JP;

Kouichirou Satou, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307279 ; 307208 ; 3072 / ; 3072 / ; 307251 ; 307289 ;
Abstract

A presettable dynamic delay flip-flop circuit including two first and second series-connected 1/2 bit delay circuits, a gate circuit for supplying these delay circuits with a control signal for controlling their operation, and a switching circuit for supplying the second delay circuit with preset data capable of freely presetting the voltage level of an output signal from said flip-flop circuit. The delay circuits and switching circuit are respectively formed of clocked inverters. The flip-flop circuit is formed of a small number of elements and operated at high frequency.


Find Patent Forward Citations

Manabe, Kenshi. (1978). Presettable dynamic delay flip-flop circuit (U.S. Patent No. 4114052). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4114052

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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