Electronic calculator or microprocessor having a selectively loadable

Abstract

An electronic calculator or microprocessor system having a selectively loadable instruction register is disclosed. The system preferably includes a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on the data stored in the data memory, an instruction memory for storing a plurality of instruction words, the instruction words controlling the operation of the system, and a program counter for addressing the instruction memory. The system is provided with a selectively loadable instruction register for temporarily storing the instruction word outputted from the instruction memory when enabled by an enabling signal. The enabling signal is provided by a first decoder logic circuit responsive to at least a portion of each instruction word outputted from the instruction memory for generating the enabling signal for a selected ones of the plurality instruction words. The system is further provided with second and third decoder logic circuits for decoding the instruction words loaded into the instruction word register and decoding the instruction words as outputted from the instruction memory, respectively. The first decoder logic circuit is preferably arranged to generate the enabling signal for loading the instruction word into the instruction word register for all instructions except BRANCH, CALL, RETURN, and DONE instructions, for instance. Preferably then when the instruction word register is not loaded with an instruction from the instruction memory because of the lack of an enabling signal, the instruction word register is preferably loaded with a no-operation instruction, the no-operation instruction permitting data to be maintained in the system's data memory.