Carry save adder

Abstract

This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the 'sum trigger' which registers the half-sum value (herein called the 'sum bit'), and the other flip-flop of the pair being the 'carry trigger' which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a 'presum' or 'precarry' bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.