Counter output detector circuit

Abstract

A counter and a memory device are included each of which includes n binary memory units. A coincident signal is outputted when the output data are coincident between the counter and the memory device. Each binary memory unit produces a binary output signal ('1' or '0') and its negated binary output signal ('1' or '0'). An exclusive OR circuit connected between the first stage memory units of the counter and the memory device. Between the corresponding memory units of the remaining each stage, and AND-OR circuit is provided being connected between a first and a second terminals. The AND-OR circuit is opened when the contents of two corresponding binary memory units are coincident. A first MOS transistor is connected between a common connection line of the first terminal and a power source. A second MOS transistor is connected between a common connection line of the second terminal and the ground. A coincident signal from the exclusive OR circuit makes the first MOS transistor conductive. The signal carried on the common connection line of the first terminal and the output signal of the exclusive OR circuit are applied to a NAND circuit. When the memory contents between the first stages are coincident and the AND-OR circuits are all opened, i.e. the contents of the counter and memory device are entirely coincident, the NAND circuit produces a coincident signal to indicate the coincidence between the output data of the counter and the memory device.